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15 Commits

Author SHA1 Message Date
Folkert Kevelam
f73a5d6958 Add logo and replace version number 2025-06-17 19:30:44 +02:00
Folkert Kevelam
12362001cd Reroute parallel bus and cleans DRC 2025-06-16 21:55:17 +02:00
Folkert Kevelam
3d8be089ea Set DRC constraints for JLCPCB 2025-06-16 21:54:58 +02:00
Folkert Kevelam
64daa151c1 Shift parallel bus a smidge 2025-06-16 21:54:31 +02:00
Folkert Kevelam
0f26005042 Initial Hardware layout 2025-06-15 22:16:46 +02:00
Folkert Kevelam
7aa72372fb Finish power and ethernet layout 2025-06-15 14:33:54 +02:00
Folkert Kevelam
bb4d3ff8f2 Lay-out Vdc 2025-06-14 21:05:20 +02:00
Folkert Kevelam
23c9bf0e17 Change to 4-layer stack-up 2025-06-14 21:05:03 +02:00
Folkert Kevelam
b0d0ae6911 Finish landscaping revision 0 2025-05-28 21:01:14 +02:00
Folkert Kevelam
7e85e76da0 Finish partial layout 2025-05-27 21:17:13 +02:00
Folkert Kevelam
674001d239 Change routing for 3v3 supply 2025-05-27 21:16:41 +02:00
Folkert Kevelam
8a8aba108e Change config options 2025-05-26 20:27:56 +02:00
Folkert Kevelam
538ccfd4bd Refit parallel bus to allow for easier routing 2025-05-26 20:27:15 +02:00
Folkert Kevelam
917b287034 Set pcb rules 2025-05-26 20:26:10 +02:00
Folkert Kevelam
ef5703bcab Reroute 3v3 power supply before P-mosfets 2025-05-26 20:24:52 +02:00
5 changed files with 61888 additions and 19148 deletions

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@ -1,19 +1,19 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"active_layer_preset": "",
"auto_track_width": false,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"images": 1.0,
"pads": 1.0,
"shapes": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
"zones": 1.0
},
"selection_filter": {
"dimensions": true,
@ -45,12 +45,13 @@
"pads",
"zones",
"drc_warnings",
"drc_exclusions",
"locked_item_shadows",
"conflict_shadows",
"shapes"
],
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
"zone_display_mode": 0
"visible_layers": "ffffffff_ffffffff_fffffff5_ffffffff",
"zone_display_mode": 1
},
"git": {
"repo_password": "",
@ -73,6 +74,8 @@
false,
false,
false,
false,
false,
false
],
"col_order": [
@ -85,7 +88,9 @@
6,
7,
8,
9
9,
10,
11
],
"col_widths": [
0,
@ -97,6 +102,8 @@
0,
0,
0,
0,
0,
0
],
"custom_group_rules": [],

View File

@ -37,9 +37,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
"drill": 3.2,
"height": 3.2,
"width": 3.2
},
"silk_line_width": 0.1,
"silk_text_italic": false,
@ -48,10 +48,16 @@
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
"min_clearance": 0.0
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
@ -102,6 +108,7 @@
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
@ -117,23 +124,23 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.1,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_copper_edge_clearance": 0.3,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_hole_clearance": 0.2,
"min_hole_to_hole": 0.2,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"min_silk_clearance": 0.15,
"min_text_height": 1.0,
"min_text_thickness": 0.15,
"min_through_hole_diameter": 0.15,
"min_track_width": 0.16,
"min_via_annular_width": 0.05,
"min_via_diameter": 0.45,
"solder_mask_to_copper_clearance": 0.1,
"use_height_for_length_calcs": true
},
"teardrop_options": [
@ -180,7 +187,16 @@
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"track_widths": [
0.0,
0.2,
0.25,
0.4,
0.5,
1.0,
2.0,
3.0
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
@ -201,13 +217,18 @@
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"max_amplitude": 0.5,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
"spacing": 0.4
}
},
"via_dimensions": [],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
@ -487,7 +508,7 @@
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"plot": "output/",
"pos_files": "",
"specctra_dsn": "",
"step": "",

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