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Set DRC constraints for JLCPCB

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This commit is contained in:
Folkert Kevelam 2025-06-16 21:54:58 +02:00
parent 64daa151c1
commit 3d8be089ea
1 changed files with 6 additions and 6 deletions
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Ethy.kicad_pro
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@ -126,7 +126,7 @@
"max_error": 0.005,
"min_clearance": 0.1,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_copper_edge_clearance": 0.3,
"min_groove_width": 0.0,
"min_hole_clearance": 0.2,
"min_hole_to_hole": 0.2,
@ -135,11 +135,11 @@
"min_resolved_spokes": 2,
"min_silk_clearance": 0.15,
"min_text_height": 1.0,
"min_text_thickness": 0.153,
"min_text_thickness": 0.15,
"min_through_hole_diameter": 0.15,
"min_track_width": 0.16,
"min_via_annular_width": 0.45,
"min_via_diameter": 0.5,
"min_via_annular_width": 0.05,
"min_via_diameter": 0.45,
"solder_mask_to_copper_clearance": 0.1,
"use_height_for_length_calcs": true
},
@ -217,10 +217,10 @@
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"max_amplitude": 0.5,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
"spacing": 0.4
}
},
"via_dimensions": [